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s 3 c 7295/p7295 product overview 1 - 1 1 product overview overview the S3C7295 single-chip cmos microcontroller has been designed for high performance using samsung's newest 4 -b it cpu core, sam47 (samsung arrangeable microcontrollers). with an up-to- 704 -dot lcd direct drive capability, and flexible 8-bit timer/counter, the S3C7295 offers an excellent design solution for a mid-end lcd game . up to 8 pins of the 80 -pin qfp package can be dedicated to i/o. six vectored interrupts provide fast response to internal and external events. in addi tion, the S3C7295 's advanced cmos technology pro vides for low power consumption. otp the S3C7295 microcontroller is also available in otp (one time programmable) version, s3p7295. s3p7295 microcontroller has an on-chip 16k-byte one-time-programable eprom instead of masked rom. the s3p7295 is comparable to S3C7295, both in function and in pin configuration.
product overview s 3 c 7295/p7295 1 - 2 features memory ? 256 4-bit ram (excluding lcd display ram) ? 16,384 8-bit rom 8 i/o pins ? i/o: 8 pins lcd controller/driver ? 44 segments and 16 common terminals (8, 12 and 16 common selectable ) ? internal resistor circuit for lcd bias ? voltage doubler ? all dot can b e switched on/off 8-bit basic timer ? 4 interval timer functions ? watch-dog timer 8-bit timer/counter ? programmable 8-bit timer ? arbitrary clock output (tclo0) ? inverted clock output ( tclo0 ) watch timer ? time interval generation: 0.5 s, 3.9 ms at 32768 hz ? four frequency outputs to buz pin and buz pin ? clock source generation for lcd interrupts ? two internal vectored interrupts ? four external vectored interrupts ? two quasi-interrupts memory-mapped i/o structure ? data memory bank 15 power-down modes ? idle mode (only cpu clock stops) ? stop mode (main system oscillation stops) ? sub system clock stop mode oscillation sources ? crystal, ceramic, or rc for main system clock ? crystal oscillator for subsystem clock ? main system clock frequency: 4.19 mhz (typical) ? subsystem clock frequency: 32.768 khz ? cpu clock divider circuit (by 4, 8, or 64) instruction execution times ? 0.95, 1.91, 15.3 s at 4.19 mhz (main) ? 122 s at 32.768 khz (subsystem) operating temperature ? ? 40 c to 85 c operating voltage range ? 2. 2 v to 3 . 4 v (0.4 mhz to 4.19 mhz) package type ? 80-pin qfp or pellet
s 3 c 7295/p7295 product overview 1 - 3 block diagram arithmetic and logic unit interrupt control block instruction register program counter program status word stack pointer instruction decoder clock reset xin xtin xout xtout internal interrupt p1.3/int p1.1/int1 p1.2/int2 p1.0/int0 i/o port 1 8-bit timer/ counter watch-dog timer i/o port 0 p0.3/buz/k3 p0.1/ /k1 p0.2/clo/ /k2 p0.0/tclo0/k0 bias ca cb seg0-seg43 com0-com15 vlc0 16k bytes program memory voltage doubler lcd driver/ controller watch timer basic timer buz tclo0 256 x 4-bit data memory figure 1-1 . S3C7295 simplified block diagram
product overview s 3 c 7295/p7295 1 - 4 pin assignments seg24 seg23 seg22 seg21 seg20 seg19 seg18 seg17 seg16 seg15 seg14 seg13 seg12 seg11 seg10 seg9 seg8 seg7 seg6 seg5 seg4 seg3 seg2 seg1 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 S3C7295 (top view) seg41 seg42 seg43 p1.3/int4 p1.2/int2 p1.1/int1 p1.0/int0 p0.3/buz/k3 p0.2/clo/ buz /k2 p0.1/ tclo 0 /k1 p0.0/tclo0/k0 vdd vss xout xin test xtin xtout reset ca cb vlc0 bias com15 com14 com13 com12 com11 com10 com9 com8 com7 com6 com5 com4 com3 com2 com1 com0 seg0 seg40 seg39 seg38 seg37 seg36 seg35 seg34 seg33 seg32 seg31 seg30 seg29 seg28 seg27 seg26 seg25 figure 1-2 . S3C7295 8 0-qfp pin assignment diagram
s 3 c 7295/p7295 product overview 1 - 5 pin descriptions table 1- 1. S3C7295 pin descriptions pin name pin type description circuit type number share pin p0.0 p0.1 p0.2 p0.3 i/o 4-bit i/o port. 1-bit and 4-bit read/write and test are possible. individual pins are software configurable as input or output. individual pins are software configurable as open- drain or push-pull output. individual pull-up resistors are software assignable; pull-up resistors are automatically disabled for output pins. e-1 11 10 9 8 tclo0 /k0 tclo0 /k1 clo / buz / k2 buz/k3 p1.0 p1.1 p1.2 p1.3 i /o same as port 0. e-1 7 6 5 4 int0 int1 int2 int4 int0, int1 i/o external interrupts. the triggering edge for int0 and int1 is selectable. 7, 6 p1.0, p1.1 int2 i/o quasi-interrupt with detection of rising or falling edges 5 p1.2 int4 i/o external interrupt with detection of rising or falling edges. 4 p1.3 buz i/o 2 khz, 4 khz, 8 khz or 16 khz frequency output for buzzer sound. 8 p0.3/k3 buz i/o inverted buz signal 9 p0.2/clo/k2 clo i/o clock output 9 p0.2/ buz /k2 tclo0 i/o inverted timer/counter 0 clock output 10 p0.1/k1 tclo0 i/o timer/counter 0 clock output 11 p0.0/k0 com0?com15 o lcd common signal output h-6 39?24 ? seg0?seg43 o lcd segment signal output h-6 40?80, 1?3 ?
product overview s 3 c 7295/p7295 1 - 6 table 1- 1. S3C7295 pin descriptions (continued) pin name pin type description circuit type number share pin k0?k3 i/o external interrupt (triggering edge is selectable) e-1 11?8 p0.0?p0.3 v dd ? p ower supply ? 12 ? v ss ? ground ? 13 ? reset i reset input (active low) b 19 ? ca, cb ? capacitor terminal for voltage doubling ? 20, 21 ? vcl0 ? lcd power supply input ? 22 ? bias o doubling voltage level output ? 23 ? x in, x out ? crystal, ceramic or rc o scillator pins for system clock ? 15, 14 ? xt in, xt out ? crystal oscill ator pins for subsystem clock ? 17, 18 ? test i test input (must be connected to v ss ) ? 16 ? note: pull-up resistors for all i/o ports are automatically disabled if they are configured to output mode.
s 3 c 7295/p7295 product overview 1 - 7 pin circuit diagrams v dd p - channel in n - channel figure 1-3. pin circuit type a v dd pull-up resistor schmitt trigger in figure 1-4 . pin circuit type b v dd resistor enable n - ch p - ch v dd pull-up resistor data output disable schmitt trigger i/o pne figure 1-5. pin circuit type e-1 v lc1 out v lc2 v lc3 seg/com data v lc0 v lc4 v ss figure 1-6 . pin circuit type h-6
s 3 c 7295/p7295 electrical data 1 3- 1 13 electrical data overview in this section, information on S3C7295 electrical characteristics is presented as tables and graphics. the information is arranged in the following order: standard electrical characteristics ? ab solute maximum ratings ? d.c. electrical characteristics ? main system clock oscillator characteristics ? subsystem clock oscillator characteristics ? i/o capacitance ? a.c. electrical characteristics ? operating voltage range miscellaneous timing waveforms ? a.c timing measurement point ? clock timing measurement at x in ? clock timing measurement at xt in ? tcl timing ? input timing for reset ? input timing for external interrupts ? serial data transfer timing stop mode characteristics and timing waveforms ? ram data retention supply voltage in stop mode ? stop mode release timing when initiated by reset ? stop mode release timing when initiated by an interrupt request
electrical data s 3 c 7295/p7295 1 3- 2 table 13- 1. absolute maximum ratings (t a = 25 c) parameter symbol conditions rating units supply voltage v dd ? ? 0.3 to + 4.5 v input voltage v i ports 0 , 1 ? 0.3 to vdd + 0.3 v output voltage v o ? ? 0.3 to vdd + 0.3 v output current high i oh one i/o p in active ? 15 ma all i/o p ins active ? 30 output current low i ol one i/o p in active + 30 (peak value) ma + 15 (note) total for p ins 0, 1 + 100 (peak value) + 60 (note) operating temperature t a ? ? 40 to + 85 c storage temperature t stg ? ? 65 to + 150 c note: the values for output current low ( i ol ) are calculated as peak value duty . table 13- 2. d.c. electrical characteristics (t a = ? 40 c to + 85 c, v dd = 2. 2 v to 3.4 v) parameter symbol conditions min typ max units input high voltage v ih1 ports 0, 1, and reset 0. 8 v dd ? v dd v v ih2 x in , x out , and xt in v dd ? 0.1 v dd input low voltage v il1 ports 0, 1, and reset ? ? 0. 2 v dd v v il2 x in , x out , and xt in 0. 1 output high voltage v oh v dd = 2. 2 v to 3.4 v i oh = ? 1 ma ports 0, 1 v dd ? 1.0 ? ? v output low voltage v ol v dd = 2. 2 v to 3.4 v i ol = 5 ma ports 0, 1 ? ? 1.0 v
s 3 c 7295/p7295 electrical data 1 3- 3 table 13-2. d.c. electrical characteristics (continued) (t a = ? 40 c to + 85 c, v dd = 2.2 v to 3.4 v) parameter symbol conditions min typ max units input high leakage current i lih1 v i = v dd all input pins except those specified below for i lih2 ? ? 3 a i lih2 v i = v dd x in , x out and xt in 20 input low leakage current i lil1 v i = 0 v all input pins except reset x in , x out and xt in ? ? ? 3 a i lil2 v i = 0 v reset, x in , x out and xt in ? 20 output high leakage current i loh v o = v dd all output pins ? ? 3 a output low leakage current i lol v o = 0 v all output pins ? ? ? 3 a pull-up resistor r l 1 v i = 0 v; v dd = 3 v po rt s 0 , 1 50 100 200 k w r l 2 v i = 0 v; v dd = 3 v ; reset 200 450 800 lcd voltage dividing resistor (1) r lcd 1 ta = + 25 c 50 100 150 k w r lcd 2 ta = + 25 c 25 50 75 ? v dd -com i ? voltage drop (i = 0?15) v dc v lc d = 3.0 v ? 15 a per common pin ? ? 120 mv ? v lc d - segx ? voltage drop (x = 0? 43 ) v ds v lc d = 3.0 v ? 15 a per common pin ? ? 120 middle output v lc0 v lc0 = 5.0 v v lc0 -0.2 v lc0 v lc0 +0.2 v voltage (2) v lc1 0.8 v lc0 -0.2 0.8 v lc0 0.8 v lc0 +0.2 v lc2 0.6 v lc0 -0.2 0.6 v lc0 0.6 v lc0 +0.2 v lc3 0.4 v lc0 -0.2 0.4 v lc0 0.4 v lc0 +0.2 v lc4 0.2 v lc0 -0.2 0.2 v lc0 0.2 v lc0 +0.2 note s : 1. rlcd1 is lcd voltage dividing resistor when lcon.2 = "0", and rlcd2 when lcon.2 = "1". 2. it is middle output voltage when 1/16 duty and 1/5 bias .
electrical data s 3 c 7295/p7295 1 3- 4 table 13- 2. d.c. electrical characteristics (concluded) (t a = ? 40 c to + 85 c, v dd = 2. 2 v to 3.4 v) parameter symbol conditions min typ max units supply current (1) i dd1 v dd = 3 v 10% 4.19 mhz (pcon=3h) crystal o scillator c1 = c2 = 22 pf ? 1.3 3.0 ma i dd2 idle mode; v dd = 3 v 10% 4.19 mhz (pcon=3h) crystal oscillator c1 = c2 = 22 pf 0.4 1.0 i dd3 ( 2 ) v dd = 3 v 10% 32 khz crystal oscillator ? 1 5 30 a i dd4 ( 2 ) idle mode; v dd = 3 v 10% 32 khz crystal oscillator 5 15 i dd5 stop mode; v dd = 3 v 10% scmod=0000b, xtin=0v 0.5 3 stop mode; v dd = 3 v 10% scmod=0100b 0.2 2 notes: 1. current in the following circuits are not included; on-chip pull-up resistors, internal lcd voltage dividing resistors, voltage doubler, and outpu t port drive currents. 2 . data includes power consumption for subsystem clock oscillation. 3 . when the system clock control register, scmod, is set to 1001b, main system clock oscillation stops and the subsystem clock is used.
s 3 c 7295/p7295 electrical data 1 3- 5 table 13- 3. main system clock oscillator characteristics (t a = ? 40 c to + 85 c, v dd = 2. 2 v to 3.4 v) oscillator clock configuration parameter test condition min typ max units ceramic oscillator xin xout c1 c2 oscillation frequency (1) ? 0.4 ? 4.19 mhz stabilization time (2) stabilization occurs when v dd is equal to the m inimum oscillator voltage range; v dd = 3.0 v ? ? 4 ms crystal oscillator xin xout c1 c2 oscillation frequency (1) ? 0.4 ? 4.19 mhz stabilization time (2) v dd = 3.0 v ? ? 10 ms external clock xin xout x in input frequency (1) ? 0.4 ? 4.19 mhz x in input high and low level width (t xh , t xl ) ? 83.3 ? 1250 ns rc oscillator xin xout r frequency v dd = 3 v 0.4 ? 1.5 mhz notes: 1. oscillation frequency and x in input frequency data are for oscillator characteristics only. 2. stabilization time is the interval required for oscilla tor stabilization after a power-on occurs, or when stop mode is terminated.
electrical data s 3 c 7295/p7295 1 3- 6 table 13-4 . recommended oscillator constants (t a = ? 40 c to + 85 c, v dd = 2. 2 v to 3.4 v) manufacturer series number (1) frequency range load cap (pf) oscillator voltage range (v) remarks c1 c2 min max tdk fcr ? e ? m5 3.58 mhz?4.2 mhz 33 33 2.2 3.4 leaded type fcr ? e ? mc5 3.58 mhz?4.2 mhz (2) (2) 2.2 3.4 on-chip c leaded type ccr ? e ? mc3 3.58 mhz?4.2 mhz (3) (3) 2.2 3.4 on-chip c smd type note s: 1. please specify normal oscillator frequency. 2. on-chip c: 30pf built in. 3. on-chip c: 38pf built in. table 13-5. subsystem clock oscillator characteristics (t a = ? 40 c to + 85 c, v dd = 2. 2 v to 3.4 v) oscillator clock configuration parameter test condition min typ max units crystal oscillator xtin xtout c1 c2 oscillation frequency (1) ? 32 32.768 35 khz stabilization time (2) v dd = 2. 2 v to 3.4 v ? 1.0 3 s external clock xtin xtout xt in input frequency (1) ? 32 ? 100 khz xt in input high and low level width (t xtl , t xth ) ? 5 ? 15 s notes: 1. oscillation frequency and xt in input frequency data are for oscillator characteristics only. 2. stabilization time is the interval required for oscillating stabili zation after a power-on occurs.
s 3 c 7295/p7295 electrical data 1 3- 7 table 13-6 . input/output capacitance (t a = 25 c, v dd = 0 v ) parameter symbol condition min typ max units input capacitance c in f = 1 mhz; unmeasured pins are returned to v ss ? ? 15 pf output capacitance c out ? ? 15 pf i/o capacitance c io ? ? 15 pf table 13-7 . voltage doubler output (t a = -40 c to + 85 c, v dd = 2.2 v to 3.4 v ) parameter symbol condition min typ max units voltage doubler output vbias v dd = 2. 2 v to 3.4 v ? 2 v dd ? v table 13-8 . a.c. electrical characteristics (t a = ? 40 c to + 85 c, v dd = 2. 2 v to 3.4 v) parameter symbol conditions min typ max units instruction cycle time ( note ) t cy v dd = 2.2 v to 3.4 v 0.95 ? 64 s with subsystem clock (fxt) 114 122 125 interrupt input high, low width f inth, f intl int0?int2, int4 k0?k3 10 ? ? reset input low wi dth t rsl input 10 ? ? note: unless otherwise specified, instruction cycle time condition values assume a main system clock ( fx ) source.
electrical data s 3 c 7295/p7295 1 3- 8 cpu clock = 1/n x oscillator frequency (n = 4, 8, 64) supply voltage (v) 15.6 khz cpu clock 1.05 mhz 4.2 mhz 1 2 3 4 5 6 7 main osc frequency (divided by 4) 2.2v figure 13- 1. standard operating voltage range table 13-9 . ram data retention supply voltage in stop mode (t a = ? 40 c to + 85 c) parameter symbol conditions min typ max unit data retention supply voltage v dddr ? 2.2 ? 3.4 v data retention supply current i dddr v dddr = 2. 2 v ? 0.1 10 a release signal set time t srel ? 0 ? ? s oscillator stabilization wait time (1) t wait released by reset ? 2 17 / fx ? ms released by interrupt ? (2) ? notes : 1. during oscillator stabilization wait time, all cpu operations must be stopped to avoid instability during oscillator start-up. 2. use the basic timer mode register (bmod) interval timer to delay execution of cpu instructions during the wait time.
s 3 c 7295/p7295 electrical data 1 3- 9 timing waveforms t srel t wait v dd reset execution of stop instruction v dddr data retention mode idle mode normal mode internal operation reset stop mode ~ ~ ~ ~ figure 13- 2. stop mode release timing when initiated b y reset reset v dd execution of stop instruction v dddr data retention mode stop mode t wait t srel idle mode normal mode power-down mode terminating signal (interrupt request) ~ ~ ~ ~ figure 13- 3. stop mode release timing when initiated b y interrupt request
electrical data s 3 c 7295/p7295 1 3- 10 0.8 v dd 0.2 v dd 0.8 v dd 0.2 v dd measurement points figure 13- 4. a.c. timing measurement points (except for x in and xt in ) x in t xl t xh 1 / f v dd - 0.5 v 0.4 v x figure 13- 5. clock timing measurement at x in xt in t xtl t xth 1 / f v dd - 0.5 v 0.4 v xt figure 13- 6. clock timing measurement at x t in
s 3 c 7295/p7295 electrical data 1 3- 11 reset t rsl 0.2 v dd figure 13-7 . input timing for reset reset signal int0, 1, 2, 4, k0 to k3 t intl t inth 0.8 v dd 0.2 v dd figure 13-8 . input timing for external interrupts
electrical data s 3 c 7295/p7295 1 3- 12 notes
s 3 c 7295/p7295 electrical data 1 3- 13 characteristic curves note the characteristic values shown in the following graphs are based on actual test measurements. they do not, however, represent guaranteed operating values. 5.0 4.5 4.0 3.5 i dd1 , i dd2 (ma) (t a = 25 c, fx = 4.2 mhz) 3.0 2.5 2.0 1.5 1.0 0.5 2.7 4.0 4.5 6.0 v dd (v) 0 i dd1 , cpu clock = fx/4 i dd1 , cpu clock = fx/64 i dd2 figure 13- 11. i dd1 , i dd2 vs. v dd
electrical data s 3 c 7295/p7295 1 3- 14 5 0 i dd3, 4, 5 (a) 2.5 v dd (v) 3.0 3.5 4.0 (t a = 25 c, fx = 32.768 khz) 10 15 20 25 30 35 40 45 4.5 5.0 5.5 6.0 6.5 i dd3 2.0 50 i dd4 i dd5 figure 13- 12. i dd3 , i dd4 , i dd5 vs. v dd
s 3 c 7295/p7295 electrical data 1 3- 15 0 . 5 0 i d d 1 ( m a ) 0 . 5 m a i n s y s t e m c l o c k f r e q u e n c y ( m h z ) 1 . 0 1 . 5 2 . 0 ( t a = 2 5 c , c p u c l o c k = f x / 4 ) 1 . 0 1 . 5 2 . 0 2 . 5 3 . 0 3 . 5 4 . 0 4 . 5 2 . 5 3 . 0 3 . 5 4 . 0 4 . 5 v d d = 6 . 0 v v d d = 4 . 5 v figure 13- 13. i dd1 vs. main system clock frequency 0 . 2 0 i d d 2 ( m a ) 0 . 5 m a i n s y s t e m c l o c k f r e q u e n c y ( m h z ) 1 . 0 1 . 5 2 . 0 ( t a = 2 5 c ) 0 . 4 0 . 6 0 . 8 1 . 0 1 . 2 1 . 4 1 . 6 2 . 5 3 . 0 3 . 5 4 . 0 4 . 5 v d d = 6 . 0 v v d d = 4 . 5 v figure 13-13 . i dd2 vs. main system clock frequency
electrical data s 3 c 7295/p7295 1 3- 16 ?2.5 0 i oh (ma) 0.5 v oh (v) 1.0 1.5 2.0 (t a = 25 c, ports 0, 2, 3, 4, 5, 6, 7) ?5.0 ?7.5 ?10.0 ?12.5 ?15.0 ?17.5 ?20.0 ?22.5 ?25.0 2.5 3.0 3.5 4.0 4.5 5.0 v dd = 4.5 v 5.5 6.0 v dd = 6.0 v figure 13 ?15. i oh vs. v oh (p0, 2, 3, 4, 5, 6, 7)
s 3 c 7295/p7295 electrical data 1 3- 17 ?2.5 0 i oh (ma) 0.5 v oh (v) 1.0 1.5 2.0 (t a = 25 c, ports 8, 9) ?5.0 ?7.5 ?10.0 ?12.5 ?15.0 ?17.5 ?20.0 ?22.5 ?25.0 2.5 3.0 3.5 4.0 4.5 5.0 v dd = 4.5 v 5.5 6.0 v dd = 6.0 v figure 13 ?16. i oh vs. v oh (p8, 9)
electrical data s 3 c 7295/p7295 1 3- 18 5.0 0 i ol (ma) 0.5 v ol (v) 1.0 1.5 2.0 (t a = 25 c, ports 0, 2, 3, 4, 5, 6, 7) 10.0 15.0 20.0 25.0 30.0 35.0 40.0 45.0 50.0 2.5 3.0 3.5 4.0 4.5 5.0 55.0 5.5 6.0 v dd = 6.0 v v dd = 4.5 v figure 13 ?17. i ol vs. v ol (p0, 2, 3, 4, 5, 6, 7)
s 3 c 7295/p7295 electrical data 1 3- 19 5.0 0 i ol (ma) 0.5 v ol (v) 1.0 1.5 2.0 (t a = 25 c, ports 8, 9) 10.0 15.0 20.0 25.0 30.0 35.0 40.0 45.0 50.0 2.5 3.0 3.5 4.0 4.5 5.0 55.0 5.5 6.0 v dd = 6.0 v v dd = 4.5 v figure 13 ?18. i ol vs. v ol (p8, 9)
s 3 c 7295/p7295 m echanical data 1 4- 1 14 mechanical data overview the S3C7295/p7295 is available in a 80-qfp-1420 package. 80-qfp-1420c #80 20.00 0.20 23.90 0.30 14.00 0.20 17.90 0.30 #1 0.80 0.35 + 0.10 note : dimensions are in millimeters. 0.15 max (0.80) 0.15 + 0.10 - 0.05 0-8 0.10 max 0.80 0.20 0.05 min 2.65 0.10 3.00 max 0.80 0.20 figure 14-1. 80-qfp-1420c package dimensions
s 3 c 7295/p7295 s3p7295 otp 15- 1 15 s3p7295 otp overview the s3p7295 single-chip cmos microcontroller is the otp (one time programmable) version of the S3C7295 microcontroller. it has an on-chip otp rom instead of masked rom. the eprom is accessed by serial data format. the s3p7295 is fully compatible with the S3C7295, both in function and in pin configuration. because of its simple programming requirements, the s3p7295 is ideal for use as an evaluation chip for the S3C7295.
s3p7295 otp s 3 c 7295/p7295 15- 2 seg24 seg23 seg22 seg21 seg20 seg19 seg18 seg17 seg16 seg15 seg14 seg13 seg12 seg11 seg10 seg9 seg8 seg7 seg6 seg5 seg4 seg3 seg2 seg1 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 s3p7295 (top view) seg41 seg42 seg43 p1.3/int4 p1.2/int2 p1.1/int1 p1.0/int0 p0.3/buz/k3 p0.2/clo/ buz /k2 sdat / p0.1/ tclo 0 /k1 sclk / p0.0/tclo0/k0 vdd / vdd vss / vss xout xin vpp / test xtin xtout reset reset / reset ca cb vlc0 bias com15 com14 com13 com12 com11 com10 com9 com8 com7 com6 com5 com4 com3 com2 com1 com0 seg0 seg40 seg39 seg38 seg37 seg36 seg35 seg34 seg33 seg32 seg31 seg30 seg29 seg28 seg27 seg26 seg25 figure 15-1. s3p7295 pin assignments (80-qfp package)
s 3 c 7295/p7295 s3p7295 otp 15- 3 table 15-1. descriptions of pins used to read/write the eprom main chip during programming pin name pin name pin no. i/o function p0.1 sdat 10 i/o serial data pin. output port when reading and input port when writing. can be assigned as a input/push-pull output port. p0.0 sclk 11 i/o serial clock pin. input only pin. test v pp (test) 16 i power supply pin for eprom cell writing (indicates that otp enters into the writing mode). when 12.5 v is applied, otp is in writing mode and when 5 v is applied, otp is in reading mode. (option) reset reset 19 i chip initialization v dd /v ss v dd /v ss 12/13 i logic power supply pin. v dd should be tied to +5 v during programming. table 15-2. comparison of s3p7295 and S3C7295 features characteristic s3p7295 S3C7295 program memory 16 kbyte eprom 16 kbyte mask rom operating voltage (v dd ) 2.2 v to 3.4 v 2.2 v to 3.4 v otp programming mode v dd = 5 v, v pp (test)=12.5v pin configuration 80 qfp 80 qfp eprom programmability user program 1 time programmed at the factory operating mode characteristics when 12.5 v is supplied to the v pp (test) pin of the s3p7295, the eprom programming mode is entered. the operating mode (read, write, or read protection) is selected according to the input signals to the pins listed in table 15?3 below. table 15-3. operating mode selection criteria v dd v pp (test) reg/mem address (a15?a0) r/w mode 5 v 5 v 0 0000h 1 eprom read 12.5 v 0 0000h 0 eprom program 12.5 v 0 0000h 1 eprom verify 12.5 v 1 0e3fh 0 eprom read protection note : "0" means low level; "1" means high level.
s3p7295 otp s 3 c 7295/p7295 15- 4 table 15-4 . d.c. electrical characteristics (t a = ? 40 c to + 85 c, v dd = 2. 2 v to 3.4 v) parameter symbol conditions min typ max units supply current (1) idd1 v dd = 3 v 10% 4.19 mhz (pcon=3h) crystal o scillator c1 = c2 = 22 pf ? 1.3 3.0 ma idd2 idle mode; v dd = 3 v 10% 4.19 mhz (pcon=3h) crystal oscillator c1 = c2 = 22 pf 0.4 1.0 idd3 ( 2 ) v dd = 3 v 10% 32 khz crystal oscillator ? 1 5 30 a idd4 ( 2 ) idle mode; v dd = 3 v 10% 32 khz crystal oscillator 5 15 idd5 stop mode; v dd = 3 v 10% scmod=0000b, xtin=0v 0.5 3 stop mode; v dd = 3 v 10% scmod=0100b 0.2 2 notes: 1. data includes power consumption for subsystem clock oscillation. 2. when the system clock control register, scmod, is set to 1001b, main system clock oscillation stops and the subsystem clock is used. 3. current in the following circuits are not included; on-chip pull-up resistors, internal lcd voltage dividing resistors, voltage doubler, and output port drive currents. cpu clock = 1/n x oscillator frequency (n = 4, 8, 64) supply voltage (v) 15.6 khz cpu clock 1.05 mhz 4.2 mhz 1 2 3 4 5 6 7 main osc frequency (divided by 4) 2.2v figure 15-2 . standard operating voltage range

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